finds any tasks with TASK_STOPPED,(include PT_TRACED), and TASK_ZOMBIE, state it

takes the corresponding actions. In case of TASK_STOPPED,it sets 0x7f in the

first 7 bits,which indicate a TASK_STOPPED state. In case of TASK_ZOMBIE,it

adjusts the task->p_opptr,original parent pointer if the task->p_pptr is

not in sync with it, readjusts the links in the Process (REMOVE_LINKS,SET_LINKS

->include/linux/sched.h), notifies the parent with a SIGCHLD before

returning,else it frees up the task_struct (hence removing the process table

entry of the Zombie,which wasnt hogging memory.) and returns with the pid of the

child process freed. In case it doesnt find any child exiting and the flags dont

contain WNOHANG,it puts itself into the wait_chldexit wait_queue,and blocks

(calls schedule() ) until the child wakes it up through a notify_parent call,and

continues again repeating the same process described above.

Memory Management related Stuff:

Physical abstraction of memory is represented by the \"struct page.\". Virtual

abstraction of the memory is evident in the vm_area_struct per process. Memory

is addressed in Pages, which are 4K on a 32 bit machine. Linux supports 3 level

page tables, even though architectures like INTEL, require only 2 levels of

Paging. As most of you might be knowing that in Protected Mode coding, the

Processors need a mechanism of translating the 32 Bit Virtual Addresses into

Physical Addresses,which are aligned on a page boundary. As mentioned before,

Linux offers 3 levels which define the course of translation of a virtual

address into a physical address. The three levels are: Page Directory a.k.a

pgd_t Page Mid Level Directory a.k.a pmd_t Page Table Entry a.k.a pte_t In a 32

bit Virtual Address Space, there has to be space for 4 GB ( 1 << 32 )

entries. This is accomplished by the 3 levels mentioned above. Every process has

a Page Directory which has PTRS_PER_PGD number of Entries, a.k.a 1024 Entries,

for 1 page of space. Each PGD entry in turn contains a pointer to a PMD

entry,which in turn contains a pointer to a PTE entry,which contains the Page

Table Entry. (or the Physical address of the Page, a.k.a __pa(addr) ) But in 2

level architectures as in INTEL, its suffice to fold the PMD entry into a PGD

entry,thereby optimising out one redundant level. Considering the fact that one

has to accomodate 4 GB of entries, Each PGD entry,gives room to hold 4 MB of